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INTEGRATED CIRCUITS
DATA SHEET
UDA1351H 96 kHz IEC 958 audio DAC
Preliminary specification File under Integrated Circuits, IC01 2000 Feb 18
Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
CONTENTS 1 1.1 1.2 1.3 1.4 1.5 2 3 4 5 6 7 8 8.1 8.2 8.3 8.4 8.5 8.5.1 8.5.2 8.5.3 8.5.4 8.5.5 8.5.6 8.6 8.6.1 8.6.2 8.7 8.7.1 8.7.2 8.7.3 8.7.4 8.7.5 8.7.6 8.7.7 8.7.8 8.7.9 FEATURES General Control IEC 958 input Digital output and input interfaces Digital sound processing and DAC APPLICATIONS GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Operating modes Clock regeneration and lock detection Mute Auto mute Data path IEC 958 input Digital data output and input interface Audio feature processor Interpolator Noise shaper The Filter Stream DAC (FSDAC) Control Static pin control mode L3 control mode L3 interface General Device addressing Register addressing Data write mode Data read mode Initialization string Overview of L3 interface registers Writable registers Readable registers 16 17 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 15.5 LIMITING VALUES
UDA1351H
THERMAL CHARACTERISTICS CHARACTERISTICS TIMING CHARACTERISTICS APPLICATION INFORMATION PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DEFINITIONS LIFE SUPPORT APPLICATIONS
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Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
1 1.1 FEATURES General
UDA1351H
* 2.7 to 3.6 V power supply * Integrated digital filter and Digital-to-Analog Converter (DAC) * Master-mode data output interface for off-chip sound processing * 256fs system clock output * 20-bit data-path in interpolator * High performance * No analog post filtering required for DAC * Supports sampling frequencies from 28 up to 100 kHz * The UDA1351H is fully pin and function compatible with the UDA1350AH. 1.2 Control 1.5 Digital sound processing and DAC
* Pre-emphasis information of IEC 958 input bitstream available in L3 interface register and on pins * Automatic de-emphasis when using IEC 958 input with 32.0, 44.1 and 48.0 kHz audio sample frequencies * Soft mute by means of a cosine roll-off circuit selectable via pin MUTE or the L3 interface * Interpolating filter (fs to 128fs) by means of a cascade of a recursive filter and a FIR filter * Third-order noise shaper operating at 128fs generates bitstream for the DAC * Filter stream digital-to-analog converter. 2 APPLICATIONS
* Controlled either by means of static pins or via the L3 microcontroller interface. 1.3 IEC 958 input
* On-chip amplifier for converting IEC 958 input to CMOS levels * Selectable IEC 958 input channel, one out of two * Lock indication signal available on pin LOCK * Lock indication signal combined on-chip with the Pulse Code Modulation (PCM) status bit; in case non-PCM has been detected pin LOCK indicates out-of-lock * Key channel-status bits available via L3 interface (lock, pre-emphasis, audio sample frequency, 2 channel PCM indication and clock accuracy). 1.4 Digital output and input interfaces
* Digital audio systems. 3 GENERAL DESCRIPTION
The UDA1351H is a single chip IEC 958 audio decoder with an integrated stereo digital-to-analog converter employing bitstream conversion techniques. Besides the UDA1351H, which is the full featured version in QFP44 package, there also exists the UDA1351TS. The UDA1351TS has IEC 958 input to the DAC only and is in SSOP28 package. The UDA1351H can operate in various operating modes: * IEC 958 input to the DAC including on-chip signal processing * IEC 958 input via the digital data output interface to the external Digital Signal Processor (DSP) * IEC 958 input to the DAC and a DSP * IEC 958 input via a DSP to the DAC including on-chip signal processing * External source data input to the DAC including on-chip signal processing.
* When the UDA1351H is clock master of the data output interfaces: - BCKO and WSO signals are output - I2S-bus or LSB-justified 16, 20 and 24 bits formats are supported. * When the UDA1351H is clock slave of the data input interface: - BCK and WS signals are input - I2S-bus or LSB-justified 16, 20 and 24 bits formats are supported.
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Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
The IEC 958 input audio data including the accompanying pre-emphasis information is available on the output data interface. A lock indication signal is available on pin LOCK indicating that the IEC 958 decoder is locked. 4 QUICK REFERENCE DATA SYMBOL Supplies VDDD VDDA IDDA(DAC) IDDA(PLL) IDDD(C) IDDD P digital supply voltage analog supply voltage analog supply current of DAC analog supply current of PLL digital supply current of core digital supply current power consumption at 48 kHz power consumption at 96 kHz General trst Tamb Vo(rms) (THD + N)/S reset active time ambient temperature - -40 note 1 - 250 - 900 -90 -60 -85 -58 100 100 96 0.1 power-on power-down at 48 kHz at 96 kHz at 48 kHz at 96 kHz at 48 kHz at 96 kHz DAC in playback mode DAC in playback mode 2.7 2.7 - - - - - - - - - - 3.0 3.0 8.0 750 0.7 1.0 16.0 24.5 2.0 3.0 80 58 109 87 PARAMETER CONDITIONS MIN.
UDA1351H
By default the DAC output and the data output interface are muted when the decoder is out-of-lock. However, this setting can be overruled in the L3 control mode.
TYP.
MAX.
UNIT
3.6 3.6 - - - - - - - - - - - - - +85 - -85 -55 -80 -53 - - - -
V V mA A mA mA mA mA mA mA mW mW mW mW s C mV dB dB dB dB dB dB dB dB
DAC in Power-down mode - DAC in Power-down mode -
Digital-to-analog converter output voltage (RMS value) total harmonic distortion-plus-noise to fi = 1.0 kHz tone at 48 kHz signal ratio at 0 dB - at -40 dB; A-weighted fi = 1.0 kHz tone at 96 kHz at 0 dB at -40 dB; A-weighted S/N signal-to-noise ratio at 48 kHz signal-to-noise ratio at 96 kHz cs Vo Note 1. The DAC output voltage is proportionally to the DAC power supply voltage. 2000 Feb 18 4 channel separation unbalance of output voltages fi = 1.0 kHz tone; code = 0; A-weighted fi = 1.0 kHz tone; code = 0; A-weighted fi = 1.0 kHz tone fi = 1.0 kHz tone - - 95 95 - 0.4 -
Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
5 ORDERING INFORMATION TYPE NUMBER UDA1351H PACKAGE NAME QFP44 DESCRIPTION plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
UDA1351H
VERSION SOT307-2
6
BLOCK DIAGRAM
handbook, full pagewidth
VDDA(DAC) CLKOUT 29 TC 23 TEST2 RTCB 39 44 VSSA VDDA 26 27 VOUTL 18
Vref VOUTR 24 22
VSSA(DAC) 17 25
VDDA(PLL) VSSA(PLL) TEST1
32 31 34
CLOCK AND TIMING CIRCUIT
DAC
DAC
VDDD(C) VSSD(C) L3MODE L3CLOCK L3DATA SELSTATIC
2 4
UDA1351H
NOISE SHAPER
INTERPOLATOR 10 6 5 35 SLICER SPDIF0 SPDIF1 SELCHAN VDDD VSSD 15 16 13 43 3 11, 14, 28, 38, 40, 41 n.c. IEC 958 DECODER DATA OUTPUT INTERFACE DATA INPUT INTERFACE 1 RESET L3 INTERFACE AUDIO FEATURE PROCESSOR 12 MUTE
21
30
42
33 BCKO
37
36
7
8 BCKI
9
19 SELCLK
20
MGL976
PREEM1 LOCK PREEM0
WSO DATAO
DATAI
WSI
SELSPDIF
Fig.1 Block diagram.
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Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
7 PINNING SYMBOL RESET VDDD(C) VSSD VSSD(C) L3DATA L3CLOCK DATAI BCKI WSI L3MODE n.c. MUTE SELCHAN n.c. SPDIF0 SPDIF1 VDDA(DAC) VOUTL SELCLK SELSPDIF LOCK VOUTR TC Vref VSSA(DAC) VSSA VDDA n.c. CLKOUT PREEM1 VSSA(PLL) VDDA(PLL) BCKO TEST1 SELSTATIC DATAO WSO n.c. TEST2 n.c. 2000 Feb 18 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 TYPE(1) DISD DS DGND DGND DIOS DIS DISD DISD DISD DIS - DID DID - AI AI AS AO DID DIU DO AO DID A AGND AGND AS - DO DO AGND AS DO DIU DIU DO DO - DISD - reset input digital supply voltage for core digital ground digital ground for core L3 interface data input and output L3 interface clock input I2S-bus data input I2S-bus bit clock input I2S-bus word select input L3 interface mode input not connected mute control input IEC 958 channel selection input not connected IEC 958 channel 0 input IEC 958 channel 1 input analog supply voltage for DAC DAC left channel analog output clock source for PLL selection input IEC 958 data selection input SPDIF and PLL lock indicator output DAC right channel analog output DESCRIPTION
UDA1351H
test pin; must be connected to digital ground (VSSD) DAC reference voltage analog ground for DAC analog ground analog supply voltage not connected clock output (256fs) IEC 958 input pre-emphasis output 1 analog ground for PLL analog supply voltage for PLL I2S-bus bit clock output test pin 1: must be connected to digital supply voltage (VDDD) static pin control selection input I2S-bus data output I2S-bus word select output not connected test pin 2; must be connected to digital ground (VSSD) not connected 6
Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
UDA1351H
SYMBOL n.c. PREEM0 VDDD RTCB Note 1. See Table 1. Table 1
PIN 41 42 43 44
TYPE(1) - DO DS DID not connected
DESCRIPTION IEC 958 input pre-emphasis output 0 digital supply voltage test pin; must be connected to digital ground (VSSD)
Pin type references DESCRIPTION digital supply digital ground analog supply analog ground digital input digital Schmitt-triggered input digital input with internal pull-down resistor digital Schmitt-triggered input with internal pull-down resistor digital input with internal pull-up resistor digital output digital input and output digital Schmitt-triggered input and output analog reference voltage analog input analog output
PIN TYPE DS DGND AS AGND DI DIS DID DISD DIU DO DIO DIOS A AI AO
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Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
UDA1351H
handbook, full pagewidth
35 SELSTATIC
42 PREEM0
36 DATAO
34 TEST1
39 TEST2
43 VDDD
44 RTCB
37 WSO
41 n.c.
38 n.c.
40 n.c.
RESET 1 VDDD(C) 2 VSSD 3 VSSD(C) 4 L3DATA 5 L3CLOCK 6 DATAI 7 BCKI 8 WSI 9 L3MODE 10 n.c. 11
33 BCKO 32 VDDA(PLL) 31 VSSA(PLL) 30 PREEM1 29 CLKOUT
UDA1351H
28 n.c. 27 VDDA 26 VSSA 25 VSSA(DAC) 24 Vref 23 TC
LOCK 21
SELCHAN 13
SPDIF0 15
SPDIF1 16
VDDA(DAC) 17
SELCLK 19
SELSPDIF 20
VOUTR 22
MUTE 12
n.c. 14
VOUTL 18
MGL977
Fig.2 Pin configuration.
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Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
8 8.1 FUNCTIONAL DESCRIPTION Operating modes DESCRIPTION IEC 958 input to the DAC
input IEC 958 CLOCK DAC
UDA1351H
MODE 1
SCHEMATIC
DSP
MGS758
2
IEC 958 input via the data output interface to the DSP
input IEC 958 CLOCK
DSP
MGS759
3
IEC 958 input to the DAC and via the data output interface to the DSP
input IEC 958 CLOCK
DAC
DSP
MGS760
4
IEC 958 input via the data output interface to the external DSP and via the data input interface to the DAC
input IEC 958 CLOCK
DAC
DSP
MGS761
5
Data input interface signal to the DAC
DAC
DSP
MGS762
The UDA1351H is a low cost multi-purpose IEC 958 decoder DAC with a variety of operating modes. In modes 1, 2, 3 and 4 the UDA1351H is clock master; it generates the clock for both the outgoing and incoming digital data streams. Consequently, any device providing data for the UDA1351H via the data input interface in mode 4 will be slave to the clock generated by the UDA1351H. In mode 5 the UDA1351H locks to signal WSI from the digital data input interface. Conforming to IEC 958, the audio sample frequency of the data input interface must be between 28.0 and 100.0 kHz.
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Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
8.2 Clock regeneration and lock detection 8.3 Mute
UDA1351H
The UDA1351H contains an on-board PLL for regenerating a system clock from the IEC 958 input bitstream or the incoming digital data stream via the data input interface. In addition to the system clock for the on-board digital sound processing the PLL also generates a 256fs clock output for use in the application. In the absence of an input signal the clock will generate a minimum frequency to warrant system functionality. Note: in case of no input signal, the PLL generates a minimum frequency and the output spectrum shifts accordingly. Since the analog output does not have a analog mute, this means noise which is out of band noise under normal operation conditions, can move into the audio band. When the on-board clock has locked to the incoming frequency the lock indicator bit will be set and can be read via the L3 interface. Internally the PLL lock indication is combined with the PCM status bit of the input data stream. When both the IEC 958 decoder and the on-board clock have locked to the incoming signal and the input data stream is PCM data, then pin LOCK will be asserted. However, when the IC is locked but the PCM status bit reports non-PCM data then pin LOCK is returned to LOW level. The lock indication output can be used, for example, for muting purposes. The lock signal can be used to drive an external analog muting circuit to prevent out of band noise to become audible in case the PLL runs at its minimum frequency (e.g. when there is no SPDIF input signal).
The UDA1351H is equipped with a cosine roll-off mute in the DSP data path of the DAC part. Muting the DAC, by pin MUTE (in static mode) or via bit MT (in L3 mode) will result in a soft mute as presented in Fig.3. The cosine roll-off soft mute takes 32 x 32 samples = 24 ms at a sampling frequency of 44.1 kHz.
handbook, halfpage
1
MGS755
mute factor 0.8
0.6
0.4
0.2
0 0 1 2 t (ms) 3
Fig.3 Mute as a function of raised cosine roll-off.
When operating in the L3 control mode the device will mute on start-up. In L3 mode it is necessary to explicitly switch off the mute for audio output by means of the MT bit in the L3 register. In the L3 mode pin MUTE does not have any function (the same holds for several other pins) and can either be left open-circuit (since it has an internal pull-down resistor) or be connected to ground.
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Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
8.4 Auto mute The extracted key parameters are: * Pre-emphasis * Audio sample frequency * Two-channel PCM indicator * Clock accuracy.
UDA1351H
By default the outputs of the digital data output interface and the DAC will be muted until the IC is locked, regardless the level on pin MUTE (in static mode) or the state of bit MT of the sound feature register (in L3 mode). In this way only valid data will be passed to the outputs. This mute is done in the SPDIF interface and is a hard mute, not a cosine roll-off mute. If needed this muting can be bypassed by setting bit AutoMT to logic 0 via the L3 interface. As a result the IC will no longer mute during out-of-lock situations. 8.5 Data path
Both the lock indicator and the key channel status bits are accessible via the L3 interface. The UDA1351H supports the following sample frequencies and data bit rates: * fs = 32.0 kHz, resulting in a data rate of 2.048 Mbits/s * fs = 44.1 kHz, resulting in a data rate of 2.8224 Mbits/s * fs = 48.0 kHz, resulting in a data rate of 3.072 Mbits/s * fs = 64.0 kHz, resulting in a data rate of 4.096 Mbits/s * fs = 88.2 kHz, resulting in a data rate of 5.6448 Mbits/s * fs = 96.0 kHz, resulting in a data rate of 6.144 Mbits/s. The UDA1351H supports timing level I, II and III as specified by the IEC 958 standard.
The UDA1351H data path consists of the slicer and the IEC 958 decoder, the digital data output and input interfaces, the audio feature processor, digital interpolator and noise shaper and the digital-to-analog converters. 8.5.1 IEC 958 INPUT
The UDA1351H IEC 958 decoder can select 1 out of 2 IEC 958 input channels. An on-chip amplifier with hysteresis amplifies the IEC 958 input signal to CMOS level (see Fig.4).
handbook, halfpage
10 nF 75
SPDIF0, 15, SPDIF1 16
180 pF
UDA1351H
MGL975
Fig.4 IEC 958 input circuit and typical application.
All 24 bits of data for left and right are extracted from the input bitstream as well as several of the IEC 958 key channel-status bits.
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Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
8.5.2 DIGITAL DATA OUTPUT AND INPUT INTERFACE
UDA1351H
* Mode selection of the sound processing bass boost and treble filters: flat, minimum and maximum * Soft mute control with raised cosine roll-off * De-emphasis selection of the incoming data stream for fs = 32.0, 44.1 and 48.0 kHz. 8.5.4 INTERPOLATOR
The digital data interface enables the exchange of digital data to and from an external signal processing device. The digital output and input formats are identical by design. The possible formats are (see Fig.5): * I2S-bus with a word length of up to 24 bits * LSB-justified with a word length of 16 bits * LSB-justified with a word length of 20 bits * LSB-justified with a word length of 24 bits. Important: the edge of the WS signal must fall on the negative edge of the BCK signal at all times for proper operation of the input and output interface (see Fig.8). In the static pin control mode the format is selected by means of pins L3MODE and L3DATA. In the L3 control mode the format defaults to the I2S-bus settings and is programmable via the L3 interface. The IEC 958 decoder provides the pre-emphasis information from the IEC 958 input bitstream to pins PREEM0 and PREEM1 and to the L3 interface register. Controlling the de-emphasis is different for the 2 modes: * Static pin control mode: - For IEC 958 input de-emphasis is automatically done, but for I2S-bus input de-emphasis is not possible. * L3 control mode: - IEC 958 input: bit SPDSEL must be set to logic 1 and de-emphasis is done automatically - I2S-bus input: bit SPDSEL must be set to logic 0 and de-emphasis can be controlled via bits DE0 and DE1. 8.5.3 AUDIO FEATURE PROCESSOR
The UDA1351H includes an on-board interpolating filter which converts the incoming data stream from 1fs to 128fs by cascading a recursive filter and a FIR filter. Table 2 Interpolator characteristics CONDITIONS 0fs to 0.45fs >0.65fs 0fs to 0.45fs - NOISE SHAPER VALUE (dB) 0.03 -50 115 -3.5
PARAMETER Pass-band ripple Stop band Dynamic range DC gain 8.5.5
The third-order noise shaper operates at 128fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted into an analog signal using a filter stream digital-to-analog converter. 8.5.6 THE FILTER STREAM DAC (FSDAC)
The FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. A post filter is not needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output. The output voltage of the FSDAC is scaled proportionally with the power supply voltage.
The audio feature processor automatically provides de-emphasis for the IEC 958 data stream in the static pin control mode and default mute at start-up in the L3 control mode. When used in the L3 control mode it provides the following additional features: * Volume control using 6 bits * Bass boost control using 4 bits * Treble control using 2 bits
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WS 1 BCK 2 3 LEFT >=8 1 2 3 RIGHT >=8 DATA MSB B2 MSB B2 I2S-BUS FORMAT WS LEFT 16 BCK 15 2 1 DATA MSB B2 B15 LSB LSB-JUSTIFIED FORMAT 16 BITS
Philips Semiconductors
96 kHz IEC 958 audio DAC
handbook, full pagewidth
MSB RIGHT 16 15 2 1 MSB B2 B15 LSB
13
WS LEFT 20 BCK 19 18 17 16 15 DATA MSB B2 B3 B4 B5 B6 WS 24 BCK 23 22 21 LEFT 20 19 18 17 16 15 DATA MSB B2 B3 B4 B5 B6 B7 B8 B9 B10
RIGHT 2 1 20 19 18 17 16 15 2 1
B19 LSB LSB-JUSTIFIED FORMAT 20 BITS
MSB
B2
B3
B4
B5
B6
B19 LSB
RIGHT 2 1 24 23 22 21 20 19 18 17 16 15 2 1
Preliminary specification
B23 LSB LSB-JUSTIFIED FORMAT 24 BITS
MSB
B2
B3
B4
B5
B6
B7
B8
B9
B10
B23 LSB
MGS752
UDA1351H
Fig.5 Digital data interface formats.
Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
8.6 Control
UDA1351H
The UDA1351H can be controlled by means of static pins or via the L3 interface. For optimum use of the features of the UDA1351H the L3 control mode is recommended since only basic functions are available in the static pin control mode. It should be noted that the static pin control mode and L3 control mode are mutual exclusive. In the static pin control mode pins L3MODE and L3DATA are used to select the format for the data output and input interface. 8.6.1 STATIC PIN CONTROL MODE
The default values for all non-pin controlled settings are identical to the default values at start-up in the L3 control mode. Table 3 PIN Pin description of static pin control mode NAME VALUE FUNCTION
Mode selection pin 35 Input pins 1 6 10 and 5 RESET L3CLOCK L3MODE and L3DATA 0 1 0 00 01 10 11 12 13 19 20 MUTE SELCHAN SELCLK SELSPDIF 0 1 0 1 0 1 0 1 Status pins 21 LOCK 0 1 30 and 42 PREEM1 and PREEM0 00 01 10 11 Test pins 23 34 39 44 TC TEST1 TEST2 RTCB 0 1 0 0 must be connected to digital ground (VSSD) must be connected to digital supply voltage (VDDD) must be connected to digital ground (VSSD) must be connected to digital ground (VSSD) clock regeneration or IEC 958 decoder out-of-lock or non-PCM data detected clock regeneration and IEC 958 decoder locked plus PCM data detected IEC 958 input: no pre-emphasis IEC 958 input: fs = 32.0 kHz with pre-emphasis IEC 958 input: fs = 44.1 kHz with pre-emphasis IEC 958 input: fs = 48.0 kHz with pre-emphasis normal operation reset must be connected to VSSD select I2S-bus format for digital data interface select LSB-justified format 16 bits for digital data interface select LSB-justified format 20 bits for digital data interface select LSB-justified format 24 bits for digital data interface normal operation mute active select input SPDIF0 (channel 0) select input SPDIF1 (channel 1) slave to fs from IEC 958; master on data output and input interfaces slave to fs from digital data input interface select data from digital data interface to DAC output select data from IEC 958 decoder to DAC output SELSTATIC 1 select static pin control mode; must be connected to VDDD
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Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
8.6.2 L3 CONTROL MODE
UDA1351H
The L3 control mode allows maximum flexibility in controlling the UDA1351H. It should be noted that in the L3 control mode several base-line functions are still controlled by pins on the device and that on start-up in the L3 control mode the output is explicitly muted by bit MT via the L3 interface. Also it should be noted that in using the L3 control mode, an initialization string is needed after power-up of the device for reliable operation. Table 4 PIN Pin description in the L3 control mode NAME VALUE FUNCTION
Mode selection pin 35 Input pins 1 5 6 10 RESET L3DATA L3CLOCK L3MODE 0 1 - - - 0 1 30 and 42 PREEM1 and PREEM0 00 01 10 11 Test pins 23 34 39 44 TC TEST1 TEST2 RTCB 0 1 0 0 must be connected to ground (VSSD) must be connected to supply voltage (VDDD) must be connected to ground (VSSD) must be connected to ground (VSSD) normal operation reset must be connected to the L3-bus must be connected to the L3-bus must be connected to the L3-bus SELSTATIC 0 select L3 control mode; must be connected to VSDD
Status pins 21 LOCK clock regeneration or IEC 958 decoder out-of-lock clock regeneration and IEC 958 decoder locked IEC 958 input: no-pre-emphasis IEC 958 input: fs = 32.0 kHz with pre-emphasis IEC 958 input: fs = 44.1 kHz with pre-emphasis IEC 958 input: fs = 48.0 kHz with pre-emphasis
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Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
8.7 8.7.1 L3 interface GENERAL
UDA1351H
Basically 2 types of data transfers can be defined: * Write action: data transfer to the device * Read action: data transfer from the device. Remark: when the device is powered up, at least one L3CLOCK pulse must be given to the L3 interface to wake-up the interface before starting sending to the device (see Fig.6). This is only needed once after the device is powered up. 8.7.2 DEVICE ADDRESSING
The UDA1351H has an L3 microcontroller interface and all the digital sound processing features and various system settings can be controlled by a microcontroller. The controllable settings are: * Restoring L3 defaults * Power-on * Selection of input channel, clock source, DAC input and external input format * Selection of filter mode and settings of treble and bass boost * Volume settings * Selection of soft mute via cosine roll-off (only effective in L3 control mode) and bypass of auto mute * Selection of de-emphasis. The readable settings are: * Mute status of interpolator * PLL locked * SPDIF input signal locked * Audio Sample Frequency (ASF) * Valid PCM data detected * Pre-emphasis of the IEC 958 input signal * ACcuracy of the Clock (ACC). The exchange of data and control information between the microcontroller and the UDA1351H is LSB first and is accomplished through a serial hardware L3 interface comprising the following pins: * L3DATA: data line * L3MODE: mode line * L3CLK: clock line. The exchange of bytes via the L3 interface is LSB first. The L3 format has 2 modes of operation: * Address mode * Data transfer mode. The address mode is used to select a device for a subsequent data transfer. The address mode is characterized by L3MODE being LOW and a burst of 8 pulses on L3CLOCK, accompanied by 8 bits (see Fig.6). The data transfer mode is characterized by L3MODE being HIGH and is used to transfer one or more bytes representing a register address, instruction or data.
The device address consists of 1 byte with: * Bits 0 and 1 (called DOM bits) representing the type of data transfer (see Table 5) * Bits 2 to 7 (address bits) representing a 6-bit device address. Table 5 Selection of data transfer DOM TRANSFER BIT 0 0 1 0 1 8.7.3 BIT 1 0 0 1 1 not used not used write data or prepare read read data
REGISTER ADDRESSING
After sending the device address, including Data Operating Mode (DOM) bits indicating whether the information is to be read or written, 1 data byte is sent using bit 0 to indicate whether the information will be read or written and bits 1 to 7 for the destination register address. Basically there are 3 methods for register addressing: 1. Addressing for write data: bit 0 is logic 0 indicating a write action to the destination register, followed by bits 1 to 7 indicating the register address (see Fig.6) 2. Addressing for prepare read: bit 0 is logic 1 indicating that data will be read from the register (see Fig.7) 3. Addressing for data read action: in this case the device returns a register address prior to sending data from that register. When bit 0 is logic 0, the register address is valid; in case bit 0 is logic 1 the register address is invalid.
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L3 wake-up pulse after power-up L3CLOCK L3MODE device address L3DATA 0 1 0
MGS753
Philips Semiconductors
96 kHz IEC 958 audio DAC
register address
data byte 1
data byte 2
DOM bits
write
Fig.6 Data write mode (for L3 version 2). 17
L3CLOCK L3MODE device address L3DATA 01 DOM bits 1 read prepare read register address 11 device address 0/1 register address data byte 1 data byte 2
Preliminary specification
valid/non-valid
UDA1351H
send by the device
MGS754
Fig.7 Data read mode.
Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
8.7.4 DATA WRITE MODE
UDA1351H
For reading data from a device, the following 6 bytes are involved (see Table 7): 1. One byte with the device address including `01' for signalling the write action to the device 2. One byte is sent with the register address from which data needs to be read; this byte starts with a `1', which indicates that there will be a read action from the register, followed again by 7 bits for the destination address in binary format with A6 being the MSB and A0 being the LSB 3. One byte with the device address including `11' is sent to the device; the `11' indicates that the device must write data to the microcontroller 4. One byte, sent by the device to the bus, with the (requested) register address and a flag bit indicating whether the requested register was valid (bit is logic 0) or invalid (bit is logic 1) 5. Two bytes, sent by the device to the bus, with the data information in binary format with D15 being the MSB and D0 being the LSB.
The data write mode is explained in the signal diagram of Fig.6. For writing data to a device, 4 bytes must be sent (see Table 6): 1. One byte starting with `01' for signalling the write action to the device, followed by the device address (`011000' for the UDA1351H) 2. One byte starting with a `0' for signalling the write action, followed by 7 bits indicating the destination address in binary format with A6 being the MSB and A0 being the LSB 3. Two data bytes with D15 being the MSB and D0 being the LSB. Note: each time a new destination register address needs to be written, the device address must be sent again. 8.7.5 DATA READ MODE
For reading data from the device, first a prepare read must be done and then data read. The data read mode is explained in the signal diagram of Fig.7. Table 6 BYTE 1 2 3 4 Table 7 BYTE 1 2 3 4 5 6 L3 write data
FIRST IN TIME L3 MODE address data transfer data transfer data transfer L3 read data FIRST IN TIME L3 MODE address data transfer address data transfer data transfer data transfer ACTION ACTION
LATEST IN TIME
BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 device address register address data byte 1 data byte 2 0 0 D15 D7 1 A6 D14 D6 0 A5 D13 D5 1 A4 D12 D4 1 A3 D11 D3 0 A2 D10 D2 0 A1 D9 D1 0 A0 D8 D0
LATEST IN TIME
BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 device address register address device address register address data byte 1 data byte 2 0 1 1 0 or 1 D15 D7 1 A6 1 A6 D14 D6 0 A5 0 A5 D13 D5 1 A4 1 A4 D12 D4 1 A3 1 A3 D11 D3 0 A2 0 A2 D10 D2 0 A1 0 A1 D9 D1 0 A0 0 A0 D8 D0
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Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
8.7.6 INITIALIZATION STRING
UDA1351H
For proper and reliable operation it is needed that the UDA1351H is initialized in the L3 control mode. This is needed to have the PLL start up after power-up of the device under all conditions. The initialization string is given in Table 8. Table 8 BYTE 1 2 3 4 5 6 7 8 L3 init string and set defaults after power-up. FIRST IN TIME L3 MODE address data transfer data transfer data transfer address data transfer data transfer data transfer init string ACTION BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 device address register address data byte 1 data byte 2 set defaults device address register address data byte 1 data byte 2 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 0 LATEST IN TIME
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96 kHz IEC 958 audio DAC
UDA1351H register map BIT FUNCTION D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Writable settings 00H system parameters default 10H sound features default 11H volume control DAC default 40H multiplex parameters default restore L3 defaults 0(1) 0(1) 0(1) 0(1) PON 1 M1 0 M0 0 CHAN IIS sel sel 0 BB3 BB2 0 0 0 BB1 0 BB0 0 VC5 0 SPD sel 1 SFOR1 SFOR0 0 TR1 0 VC4 0 0 TR0 0 VC3 0 DE1 0 VC2 0 DE0 0 VC1 0 Auto MT 1 MT 1 VC0 0 RST PLL 0
Readable settings interpolator parameters SPDIF input and lock parameters PLL lock SPD lock ASF1 ASF0 PCM stat PRE ACC1 MT stat ACC0
UDA1351H
Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
8.7.8 WRITABLE REGISTERS Table 13 DAC input selection SPD sel 0 1
UDA1351H
8.7.8.1
Restoring L3 defaults
FUNCTION input from data input interface input from IEC 958 (default setting)
By writing to the 7FH register, all L3 control values are restored to their default values. Only the L3 interface is affected, the system will not be reset. Consequently readable registers, which are not reset, can be affected.
8.7.8.6
Serial format selection
8.7.8.2
Power-on
A 1-bit value to switch the DAC on and off. Table 10 Power-on setting PON 0 1 power-down power-on (default setting) FUNCTION
A 2-bit value to set the serial format for the digital data output and input interfaces. Table 14 Serial format settings SFOR1 SFOR0 0 0 1 1 0 1 0 1 FUNCTION I2S-bus (default settings) LSB-justified, 16 bits LSB-justified, 20 bits LSB-justified, 24 bits
8.7.8.3
Slicer input selection
A 1-bit value to select an IEC 958 input channel. Table 11 Slicer input selection CHAN sel 0 1 FUNCTION IEC 958 input from pin SPDIF0 (default setting) IEC 958 input from pin SPDIF1
8.7.8.7
Filter mode selection
A 2-bit value to program the mode for the sound processing filters of bass boost and treble. Table 15 Filter mode settings M1 0 0 1 1 M0 0 1 0 1 maximum minimum FUNCTION flat (default setting)
8.7.8.4
Clock source selection
A 1-bit value to select the source for clock regeneration, either from the IEC 958 input or digital data input interface. In the event that the IEC 958 input is used as a clock source the UDA1351H is clock master on the digital data output and input interfaces. Table 12 Clock source selection IIS sel 0 1 FUNCTION slave to audio sampling frequency of IEC 958 input (default setting) slave to audio sampling frequency of digital data input interface
8.7.8.8
Treble
A 2-bit value to program the treble setting in combination with the filter mode settings. At fs = 44.1 kHz the -3 dB point for minimum setting is 3.0 kHz and the -3 dB point for maximum setting is 1.5 kHz. The default value is `00'. Table 16 Treble settings LEVEL TR1 0 0 1 1 TR0 FLAT (dB) 0 1 0 1 0 0 0 0 MIN. (dB) 0 2 4 6 MAX. (dB) 0 2 4 6
8.7.8.5
DAC input selection
A 1-bit value to select the data source, either the IEC 958 input or the digital data input interface.
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Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
8.7.8.9 Bass boost 8.7.8.11 Soft mute
UDA1351H
A 4-bit value to program the bass boost setting in combination with the filter mode settings. At fs = 44.1 kHz the -3 dB point for minimum setting is 250 Hz and the -3 dB point for maximum setting is 300 Hz. The default value is `0000'. Table 17 Bass boost settings LEVEL BB3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BB2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BB1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BB0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 FLAT (dB) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIN. (dB) 0 2 4 6 8 10 12 14 16 18 18 18 18 18 18 18 MAX. (dB) 0 2 4 6 8 10 12 14 16 18 20 22 24 24 24 24
A 1-bit value to enable the digital mute. Table 19 Soft mute selection MT 0 1 no muting muting (default setting) FUNCTION
8.7.8.12
Volume control
A 6-bit value to program the left and right channel volume attenuation. The range is from 0 to -60 dB and - dB in steps of 1 dB. Table 20 Volume settings VC5 0 0 0 0 : 1 1 1 1 1 1 1 1 1 1 1 1 1 VC4 0 0 0 0 : 1 1 1 1 1 1 1 1 1 1 1 1 1 VC3 0 0 0 0 : 0 0 0 0 0 1 1 1 1 1 1 1 1 VC2 0 0 0 0 : 0 1 1 1 1 0 0 0 0 1 1 1 1 VC1 0 0 1 1 : 1 0 0 1 1 0 0 1 1 0 0 1 1 VC0 0 1 0 1 : 1 0 1 0 1 0 1 0 1 0 1 0 1 -60 - -57 VOLUME (dB) 0 0 -1 -2 : -51 -52 -54
8.7.8.10
De-emphasis
A 2-bit value to enable the digital de-emphasis filter. Table 18 De-emphasis selection DE1 0 0 1 1 DE0 0 1 0 1 fs = 32.0 kHz fs = 44.1 kHz fs = 48.0 kHz FUNCTION other (default setting)
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Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
8.7.8.13 Auto mute 8.7.9.2 PLL lock detection
UDA1351H
A 1-bit value to activate mute during out-of-lock. In normal operation the output is automatically hard muted when an out-of-lock situation is detected. Setting this bit to logic 0 will disable that function. Table 21 Auto mute setting Auto MT 0 1 FUNCTION do not mute output during out-of-lock mute output during out-of-lock (default setting)
A 1-bit value indicating that the clock regeneration is locked. Table 24 PLL lock indication PLL lock 0 1 out-of-lock locked FUNCTION
8.7.9.3
SPDIF lock detection
8.7.8.14
PLL reset
A 1-bit value indicating the IEC 958 decoder is locked and is decoding correct data. Table 25 SPDIF lock detection SPD lock 0 1 FUNCTION not locked or non-PCM data detected locked and PCM data detected
A 1-bit value to reset the PLL. This is the bit which is set in the initialization string. When this bit is asserted, the PLL will be reset and the output clock of the PLL will be forced to its lowest value, which is in the area of a few MHz. Table 22 PLL reset RST PLL 0 1 8.7.9 PLL is reset FUNCTION normal operation (default)
8.7.9.4
Audio sample frequency detection
A 2-bit value indicating the audio sample frequency of the IEC 958 input signal. Table 26 Audio sample frequency detection ASF1 0 0 1 1 ASF0 0 1 0 1 44.1 kHz undefined 48.0 kHz 32.0 kHz FUNCTION
READABLE REGISTERS
8.7.9.1
Mute status
A 1-bit value indicating whether the interpolator is muting or not muting. Table 23 Interpolator mute status MT stat 0 1 no muting muting FUNCTION
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Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
8.7.9.5 PCM detection 8.7.9.7 Clock accuracy detection
UDA1351H
A 1-bit value which indicates whether the IEC 958 input contains PCM audio data or other binary data. Table 27 Two-channel PCM input detection PCM stat 0 1 FUNCTION input with 2 channel PCM data input without 2 channel PCM data
A 2-bit value indicating the timing accuracy of the IEC 958 input signal is conforming to the IEC 958 specification. Table 29 Input signal accuracy detection ACC1 0 0 1 1 ACC0 0 1 0 1 level II level I level III undefined FUNCTION
8.7.9.6
Pre-emphasis detection
A 1-bit value which indicates whether the pre-emphasis bit was set on the IEC 958 input signal or not set. Table 28 Pre-emphasis detection PRE 0 1 FUNCTION no pre-emphasis pre-emphasis
9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD Txtal Tstg Tamb Ves Ilu(prot) Isc(DAC) PARAMETER supply voltage crystal temperature storage temperature ambient temperature electrostatic handling voltage latch-up protection current short-circuit current of DAC Human Body Model (HBM); note 2 Machine Model (MM) note 3 note 4 output short-circuited to VSSA(DAC) output short-circuited to VDDA(DAC) Notes 1. All VDD and VSS connections must be made to the same power supply. 2. JEDEC class 2 compliant, except pin VSSA(PLL) which can withstand ESD pulses of -1600 to +1600 V. 3. Latch-up test at Tamb = 125 C and VDD = 3.6 V. 4. Short-circuit test at Tamb = 0 C and VDD = 3 V. DAC operation after short-circuiting cannot be warranted. 10 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 63 UNIT K/W - - 482 346 mA mA note 1 CONDITIONS MIN. 2.7 -25 -65 -40 -2000 -200 - MAX. 5.0 +150 +125 +85 +2000 +200 200 V C C C V V mA UNIT
2000 Feb 18
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Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
UDA1351H
11 CHARACTERISTICS VDDD = VDDA = 3.0 V; IEC 958 input with fs = 48.0 kHz; Tamb = 25 C; RL = 5 k; all voltages measured with respect to ground; unless otherwise specified. SYMBOL Supplies; note 1 VDDA VDDA(DAC) VDDA(PLL) VDDD VDDD(C) IDDA(DAC) IDDA(PLL) IDDD(C) IDDD P analog supply voltage analog supply voltage for DAC analog supply voltage for PLL digital supply voltage digital supply voltage for core analog supply current of DAC analog supply current of PLL digital supply current of core digital supply current power consumption at 48 kHz power consumption at 96 kHz Digital input pins VIH VIL Vhys(RESET) ILI Ci Rpu(int) Rpd(int) VOH VOL IL(max) Vref Vo(rms) HIGH-level input voltage LOW-level input voltage hysteresis voltage on pin RESET input leakage current input capacitance internal pull-up resistance internal pull-down resistance IOH = -2 mA IOL = 2 mA 0.8VDD -0.5 - - - 16 16 - - 0.8 - - 33 33 - - 3 VDD + 0.5 V +0.2VDD - 10 10 78 78 - 0.4 - V V A pF k k power-on power-down at 48 kHz at 96 kHz at 48 kHz at 96 kHz at 48 kHz at 96 kHz DAC in playback mode DAC in Power-down mode DAC in playback mode DAC in Power-down mode 2.7 2.7 2.7 2.7 2.7 - - - - - - - - - - - - 3.0 3.0 3.0 3.0 3.0 8.0 750 0.7 1.0 16.0 24.5 2.0 3.0 80 58 109 87 3.6 3.6 3.6 3.6 3.6 - - - - - - - - - - - - V V V V V mA A mA mA mA mA mA mA mW mW mW mW PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Digital output pins HIGH-level output voltage LOW-level output voltage maximum load current 0.85VDD - - measured with respect to VSSA note 3 V V mA
Digital-to-analog converter; note 2 reference voltage output voltage (RMS value) 0.45VDDA 0.50VDDA 0.55VDDA V - 900 - mV
2000 Feb 18
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Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
UDA1351H
SYMBOL
PARAMETER
CONDITIONS fi = 1.0 kHz tone at 48 kHz at 0 dB at -40 dB; A-weighted fi = 1.0 kHz tone at 96 kHz at 0 dB at -40 dB; A-weighted - - - -
MIN.
TYP. -90 -60 -85 -58 100 100 96 0.1
MAX. -85 -55 -80 -53 - - - - 3.3 - -
UNIT dB dB dB dB dB dB dB dB
(THD + N)/S total harmonic distortion-plus-noise to signal ratio
S/N
signal-to-noise ratio at 48 kHz signal-to-noise ratio at 96 kHz
fi = 1.0 kHz tone; code = 0; 95 A-weighted fi = 1.0 kHz tone; code = 0; 95 A-weighted fi = 1.0 kHz tone fi = 1.0 kHz tone - 0.4
cs Vo Vi(p-p) Ri Vhys Notes
channel separation unbalance of output voltages
IEC 958 inputs AC input voltage (peak-to-peak value) input resistance hysteresis voltage 0.2 - - 0.5 6 40 V k mV
1. All supply pins VDD and VSS must be connected to the same external power supply unit. 2. When the DAC must drive a higher capacitive load (above 50 pF), then a series resistor of 100 must be used in order to prevent oscillations in the output stage of the operational amplifier. 3. The output voltage of the DAC is proportional to the DAC power supply voltage. 12 TIMING CHARACTERISTICS VDDD = VDDA = 2.7 to 3.6 V; Tamb = -40 to +85 C; RL = 5 k; all voltages measured with respect to ground; unless otherwise specified. SYMBOL Device reset trst tlock reset active time - fs = 32.0 kHz fs = 44.1 kHz fs = 48.0 kHz fs = 96.0 kHz I2S-bus Tcy(BCK) tBCKH tBCKL tr timing (see Fig.8) bit clock cycle time bit clock HIGH time bit clock LOW time rise time Ts = cycle time of sample frequency - 140 140 - - - - -
1 64Ts
PARAMETER
CONDITIONS
MIN.
TYP. - - - - -
MAX.
UNIT s ms ms ms ms
250
PLL lock time time to lock - - - - 85.0 63.0 60.0 40.0
s ns ns ns
280 280 20
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Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
UDA1351H
SYMBOL tf tsu(WS) th(WS) tsu(DATAI) th(DATAI) th(DATAO) td(DATAO-BCK) td(DATAO-WS) fall time
PARAMETER set-up time word select hold time word select set-up time data input hold time data input hold time data output data output to bit clock delay data output to word select delay
CONDITIONS - 20 10 20 0 0 - -
MIN. - - - - - - - -
TYP. - - - - -
MAX. 20
UNIT ns ns ns ns ns ns ns ns
80 80
Microcontroller L3 interface timing (see Figs 9 and 10) Tcy(CLK)(L3) tCLK(L3)H tCLK(L3)L tsu(L3)A th(L3)A tsu(L3)D th(L3)D t(stp)(L3) tsu(L3)DA L3CLOCK cycle time L3CLOCK HIGH time L3CLOCK LOW time L3MODE set-up time in address mode L3MODE hold time in address mode L3MODE set-up time in data transfer mode L3MODE hold time in data transfer mode L3MODE stop time in data transfer mode L3DATA set-up time in address and data transfer mode L3DATA hold time in address and data transfer mode L3DATA set-up time in data transfer mode L3DATA hold time in data transfer mode read mode read mode 500 250 250 190 190 190 190 190 190 - - - - - - - - - - - - - - - - - - ns ns ns ns ns ns ns ns ns
th(L3)DA tsu(L3)R th(L3)R
30 50 360
- - -
- - -
ns ns ns
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Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
UDA1351H
handbook, full pagewidth
WS t BCKH t h(WS) t su(WS) BCK t BCKL Tcy(BCK) DATAO t d(DATAO-BCK)
tr
tf
t d(DATAO-WS)
t h(DATAO)
t su(DATAI) t h(DATAI) DATAI
MGS756
Fig.8 I2S-bus timing of output and input interface.
handbook, full pagewidth
L3MODE th(L3)A tCLK(L3)L tsu(L3)A L3CLOCK tCLK(L3)H th(L3)A tsu(L3)A
Tcy(CLK)(L3) tsu(L3)DA th(L3)DA
L3DATA
BIT 0
BIT 7
MGL723
Fig.9 Timing for address mode.
2000 Feb 18
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Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
UDA1351H
handbook, full pagewidth
tstp(L3)
tstp(L3)
L3MODE tCLK(L3)L tsu(L3)D tCLK(L3)H Tcy(CLK)L3 th(L3)D
L3CLOCK
th(L3)DA L3DATA write
tsu(L3)DA
th(L3)DA
BIT 0
BIT 7
L3DATA read ten(L3)DA th(L3)R tsu(L3)R tdis(L3)DA
MGL889
Fig.10 Timing for data transfer mode.
2000 Feb 18
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andbook, full pagewidth
X1-31
VDDA(PLL) X1-32
X1-29
X1-28
X1-39
X1-38
X1-40
X1-41
VDDA(DAC) X1-17
VDDD(C) VDDA L27 VDDD(C) BZN32A07 C11 100 F (16 V) C41 100 nF (50 V)
X1-34 X1-27 X1-26 X1-2 X1- 4 X1-6 X1-10
TEST1 VDDA VSSA VDDD(C) VSSD(C) L3CLOCK L3MODE L3DATA
31 34 27 26 2 4 6 10 5
32
29
28
39
38
40
41
17
VSSA(DAC) X1-25
VSSA(PLL)
CLKOUT
TEST2
n.c.
n.c.
n.c.
n.c.
PREEM0
PREEM1
VDDD
SELCLK
ground AGND +3 V DGND J1 J3 J2 C3 100 F (16 V) C5 100 F (16 V) VDDA VDDD(C) VDDD VDDD R38 1 C9 100 F (16 V)
X1-20 SELSPDIF
DATAO
DATAI
BCKO
BCKI
VSSD
LOCK
WSO
WSI
X1-42
X1-43
X1-30
X1-36
X1-21
X1-37
X1-33
X1-19
X1-7
X1-8
X1-3
X1-9
2000 Feb 18 30
13 APPLICATION INFORMATION
Philips Semiconductors
96 kHz IEC 958 audio DAC
clock output VDDA
L26 BZN32A07 C12 100 F (16 V) C42 100 nF (50 V)
L29 C43 100 nF (50 V) BZN32A07 C14 100 F (16 V) VDDA
25 24
Vref
X1-24 C44 100 nF (50 V) C13 10 F (16 V)
1
RESET
X1-1
C40 VDDD(C) 100 nF (50 V)
12 11 14
MUTE n.c. n.c.
X1-12 X1-11 X1-14
VDDD(C)
3 2 1
J26 mute no mute
L3-bus X1-5 J14 3 static 2 1 L3 X16 IEC channel 0 X11 R41 75 C48 180 pF (50 V) VDDD(C) C45 10 nF (50 V)
X1-35
SELSTATIC
35
UDA1351H
44
RTCB
X1-44
VDDD(C)
3 2 1
J17 1 RTCB 0 J25 1 TC 0 X18 output left X13
X1-15
SPDIF0
15 23 TC X1-23
VDDD(C)
3 2 1
X17 IEC channel 1 X12 R42 75 C49 180 pF (50 V)
C46 10 nF (50 V)
X1-16
SPDIF1
18 16
VOUTL X1-18
C15 47 F (16 V)
R44 R43 10 k 100
J28 3 SPDIF1 2 SPDIF0
1
VDDD(C)
X1-13
SELCHAN
13 43 3 21 42 30 36 37 33 7 8 9 19 20
22
VOUTR X1-22
C16 47 F (16 V)
R46 R45 10 k 100
X19 output right X14
Preliminary specification
VDDD(C)
C28 100 nF (50 V) lock
R39 1 k V5
3 2 1
J32 data IEC data I2S-bus J31 clock I2S-bus clock IEC
UDA1351H
preemphasis indication
I2S-bus output
I2S-bus input
VDDD(C)
AGND DGND
3 2 1
MGL978
Fig.11 Test and application diagram.
Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
14 PACKAGE OUTLINE QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
UDA1351H
SOT307-2
c
y X
A 33 34 23 22 ZE
e E HE wM bp pin 1 index 44 1 bp D HD wM 11 ZD B vM B vMA 12 detail X A A2 (A 3) Lp L
A1
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.10 A1 0.25 0.05 A2 1.85 1.65 A3 0.25 bp 0.40 0.20 c 0.25 0.14 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.8 HD 12.9 12.3 HE 12.9 12.3 L 1.3 Lp 0.95 0.55 v 0.15 w 0.15 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 10 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT307-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 97-08-01
2000 Feb 18
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Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
15 SOLDERING 15.1 Introduction to soldering surface mount packages
UDA1351H
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 15.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. 15.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. 15.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
15.5 Suitability of surface mount IC packages for wave and reflow soldering methods
UDA1351H
SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 16 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 17 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable
2000 Feb 18
33
Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
NOTES
UDA1351H
2000 Feb 18
34
Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
NOTES
UDA1351H
2000 Feb 18
35
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2000
Internet: http://www.semiconductors.philips.com
SCA 69
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753503/25/01/pp36
Date of release: 2000
Feb 18
Document order number:
9397 750 06659

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